1. Field of the Invention
The present invention relates to a thin film transistor, a liquid crystal display using this thin film transistor, and a method of manufacturing the thin film transistor. More specifically, the present invention relates to a thin film transistor with improved on-current and channel length, a liquid crystal display using this thin film transistor, and a method of manufacturing this thin film transistor.
2. Description of the Related Art
Liquid crystal displays using thin film transistors (TFTs) as switching elements have widely spread. An inverted staggered structure is adopted in many amorphous silicon (a-Si) TFTs. While TFTs are classified into a channel protection type or a channel etch type, the channel etch type is the mainstream today in order to reduce the number of manufacturing steps.
Although a method of manufacturing a channel etch type TFT realizable by using five or six masks has been conventionally applied, a method of manufacturing a channel etch type TFT realizable by using four masks has been disclosed in order to further reduce the number of manufacturing steps.
For example, according to Japanese Laid-open Patent No. 2000-164886, the number of manufacturing steps is reduced by using a photosensitive film, which is formed thinly at a channel region of a TFT and formed thickly in source and drain electrode formation regions, while removing the photosensitive film in other regions, so as to isolate source and drain electrodes made of the same metal layer. Firstly, a conductive layer is formed on an insulating substrate, and the conductive layer is patterned to form a gate wiring by use of a first photomask while applying the photo-lithographic technique and the etching technique. A gate insulating film is formed on the gate wiring and a semiconductor layer, an n+ doped semiconductor layer, and source and drain metal layers are laminated. Subsequently, a photosensitive film is formed thickly on a source electrode formation region and on a drain electrode formation region and is formed thinly on a region between the source and the drain electrode formation regions by use of a second photomask and the photo-lithographic technique. Further, the source and drain metal layers, the n+ doped semiconductor layer, and the semiconductor layer are etched by using this photosensitive film as a mask to pattern the source and drain electrodes, the n+ doped semiconductor layer, and the semiconductor layer. At the same time as the etching of the n+ doped semiconductor layer and the semiconductor layer, the thickness of the photosensitive film is reduced by removing controlled amount of the thin photosensitive layer in the region between the source and the drain electrode formation regions.
The photosensitive film on the source and drain electrode formation regions is reduced in the thickness but still remains thereon. By etching the source and drain metal layers exposed between the source and drain electrode formation regions and further etching the n+ doped semiconductor layer between the source and drain electrode formation regions, the source and drain electrodes as well as the n+ doped semiconductor layer are patterned. Then, the photosensitive film is removed.
Next, a passivation layer is formed and then a contact hole is formed by use of a third photomask while applying the photo-lithographic technique and the etching technique. Subsequently, a transparent conductive film is formed and a pixel electrode is formed by use of a fourth photomask while applying the photo-lithographic technique and the etching technique.
Above mentioned photosensitive film will be described at photo-resist, hereafter.
Meanwhile, Japanese Laid-open Patent No. 2001-324725 discloses a photomask pattern, which is configured to form a photo-resist pattern thickly at source and drain electrode formation regions and to form the photo-resist pattern thinly at a region between the source and drain electrode formation regions. As shown in FIG. 1A, this photomask pattern includes two light shielding regions 111a for covering to form source and drain electrodes, and an narrow rectangular light shielding portion 112a disposed between the two light shielding regions 111a while respectively interposing slits 113a. Exposure is performed by use of the above-described photomask pattern. Based on the understanding that there arises a problem that there becomes non uniform in thickness a thin photo-resist pattern in a channel region between the source and drain electrode formation regions when using the above-described mask pattern, there is also disclosed a photomask pattern includes light shielding regions 111b having cut-off corners on both ends as shown in FIG. 1B, for example. A photo-resist pattern is formed by use of the above-described photomask pattern, and then a metal layer, an n+ a-Si layer, and an a-Si layer are etched to pattern source and drain electrodes, the a-Si layer, and the n+ a-Si layer. Thereafter, a thin portion of the photo-resist pattern between the source and drain electrode formation regions is removed. Further, the n+ a-Si layer and the a-Si layer are etched by using the separated photo-resist pattern as a mask.
Meanwhile, Japanese Laid-open Patent No. 2002-55364 also discloses photomask patterns in various shapes. For example, as shown in FIG. 2A, there is disclosed a photomask pattern including a plurality of narrow rectangular light shielding portions 112d arranged while interposing slits 113d between two light shielding regions 111d. When a thin film transistor is manufactured by use of this photomask pattern, a semiconductor film 104 above a gate electrode 102 and between a source electrode 106a and a drain electrode 106b, i.e. each endportion of a channel region in the semiconductor film 104, is formed in a bent manner due to a light interference phenomenon, as shown in FIG. 2C. In this specification, such end portions of a channel region of a TFT will be here in after referred to as both edge portions. When bending occurs in both edge portions of this semiconductor film 104, a path of an on-current of the TFT is also flexed. Accordingly, image quality of a liquid crystal display formed by arranging such TFTs in a matrix will be degraded. To prevent occurrence of the flexure on the both edge portions, there is also disclosed a technique to form a wide semiconductor film 104 as shown in FIG. 2D by use of a photomask pattern in the shape as shown in FIG. 2B, for example.
Moreover, Japanese Laid-open Patent No. 2002-57338 discloses that uniformity of the thickness of the thin photo-resist pattern for forming the channel region between the source and drain electrode formation regions is degraded by use of the above-described photomask pattern shown in FIG. 1A. In addition, this gazette also discloses problems that unevenness in the channel length among the TFTs is increased when using the photomask pattern as shown in FIG. 1A due to nonuniformity of the film thickness of the photo-resist pattern, and that display characteristic of a liquid crystal display is degraded as a consequence. To solve these problems, there is disclosed an improvement in the shape of light shielding regions 111c of the photomask pattern as shown in FIG. 1C.
Incidentally, each of these photomask patterns includes a light transparent portion, the light shielding region, and a semi-transparent region which is made up of a light transparent and light shielding pattern below resolution ability of an exposure apparatus. Light transmission amount of this semi-transparent region is susceptible to unevenness of the photomask pattern caused in manufacturing. For example, in the photomask pattern shown in FIG. 1B, each endportion of an aperture slit is formed wider than the center portion of the aperture slit, while width of a semi-transparent region is selected equal to or narrower than the resolution ability of the exposure apparatus. In particular, the influence of unevenness of the photomask pattern caused in manufacturing is more significant at the end portion as compared to the center of the aperture slit. Accordingly, the light transmission amount in the semi-transparent region is different between the center and the end portion of the aperture slit. Therefore, there is a problem that the thickness of the photo-resist pattern formed in the semi-transparent region becomes non uniform.
Meanwhile, in the photomask pattern shown in FIG. 2B, the semi-transparent portion inside the channel region includes the aperture slits and the light shielding regions which are longitudinally aligned, and the both edge portions on an upper part and on a lower part of the channel region include the aperture slits and the light shielding regions which are laterally aligned. If the dimensional accuracy of the photomask pattern in terms of the longitudinal direction is different from the dimensional accuracy in terms of the lateral direction, the thickness of the photo-resist pattern formed inside the channel region is different from the thickness of the photo-resist pattern formed on the both edge portions to be formed on the upper part and the lower part of the channel region. If the thickness of the photo-resist at a center portion of the channel region is different from the thickness of the photo-resist at the both edge portions thereof, expansion amounts of the channel length and a channel width fluctuate due to variation in an exposure amount, and it is therefore difficult to stabilize on-current characteristic of the TFT. For example, when the thickness of the photo-resist at the both edge portions becomes thinner than the thickness of the photo-resist at center portion of the channel region, the exposure amount most suitable for the channel length fluctuates and the on-current of the TFT is thereby reduced. On the contrary, when the thickness of the photo-resist at the both edge portions becomes thicker than the thickness of the photo-resist at center portion of the channel region, the on-current of the TFT is increased but it is necessary to secure a sufficient interval from the channel width to an end of a gate electrode. Accordingly, it is necessary to elongate a gate electrode. When this gate electrode is elongated, the area occupied by the TFT is spread while an aperture ratio is reduced. Therefore, it is preferable to set both dimensional accuracy in the longitudinal direction of the photomask pattern and in the lateral direction thereof to the same degree, and it is necessary to strictly manage the unevenness of the photomask in manufacturing.
In addition, when light is irradiated from a transparent insulating substrate side, an off-current of the TFT, i.e. a light leak current is increased when the light reaches the a-Si layer in the vicinity of the drain electrode without being shielded by the gate electrode. As shown in FIG. 2D, in the TFT formed by use of the photomask of FIG. 2B, each portion of the a-Si layer protruding beyond the drain electrode and located outside of the gate electrode contributes to generation of the leak current. Accordingly, the light leak current is further increased.
Meanwhile, in the mask pattern shown in FIG. 1C, aprotruded portion is formed in a narrow rectangular portion 112cin the vicinity of an end portion of the aperture slit 113c, while a width of the light transparent region is selected equal to or below the resolution ability of the exposure apparatus. However, the influence of the unevenness of the photomask pattern in manufacturing is larger at the protruded portion in the vicinity of the end portion of the aperture slit 113c than in the center portion thereof. Accordingly, a problem similar to the case using the mask pattern shown in FIG. 1B arises.